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Logic Decomposition With Technolgy Mapping for Area and Delay Minimization in Fpga Design


Author

Dayo, Khalil-Ur-Rehman

Program

PhD

Institute

Mehran University of Engineering & Technology

City

Jamshoro

Province

Sindh

Country

"Pakistan"

Thesis Completing Year

2006

Thesis Completion Status

Completed

Subject

Physics

Language

English

Keywords


Natural Sciences; Physics; Electricity & electronics; Telecommunication engineering

Link

http://prr.hec.gov.pk/jspui/bitstream/123456789/6614/1/3382H.pdf

ID

ARI-71210

Added

2021-02-17 07:49:13

Modified

0000-00-00 00:00:00