سوشل میڈیا کا استعمال اخلاقیات اور شریعت کے نکتہ نظر سے: ایک تفصیلی جائزہ

Throughout the history humanity has witnessed many ups and downs. There might have been many eras of moral lawlessness in which humanity might have suffered from lack of moral character, civilization, lack of social norms and values and many such things. But in the present era social media has emerged as a very sharp sword which has destroyed social values, norms and morality. It has proven destructive to a unprecedented level. Sometimes people share news about a person without conformation and on other times people destroy human shapes and give them resemblance with animal shapes and then share them on social media by way of comparison between human and animals. Insulting political opponents, playing with honor and dignity of others, humiliating others have become a game to play for people on social media. Many users of the social media think that there is no respect for others at all so they don’t hesitate from humiliating people. For them the only act worth doing is to protect the so called respect of the leader they follow and love. They are ready to cross any limit for this.  While doing all this they forget anything and everything about civility, morality, and social values etc. Someone has quite rightly said that good character is proof of good blood. While using social media one is in fact representing one’s family and blood. According to statistics 58% of the whole population of our country consists of young people the majority of which is so much attached and engrossed with the use of social media that they are oblivious of what is going around them. The spell of social media has bound people in the galleries of hospitals, pathways, passengers, and in educational institutes. So much so that even in homes, social media has preoccupied people to an extent that they damn care for the people living in the same home with them. There is value for a friend on social media but there is no value for a person sitting very next to them. A young man is busy and engaged with a so called sister on social media but his real sister is seen tantalized for his care and affection. In the university students miss out lectures of teacher but want to learn things from google and social media. This is the dilemma of the current age. The use of social media has taken people far away from the people sitting and living very close to them. Now the young generation has options i.e. Positive or negative use of social media. Your face book account, your profile is reflective of your personality. Any visitor, while visiting your profile and account will have your whole personality open up to him. Difference of opinion is permitted and appreciable thing but it should be done within limits. The current research paper is an attempt to cover up all these things and to see the Islamic teachings about the use of social media. How to open an account on social media, how to share pictures on it either self or that of others, sending friend requests and accepting them? These and other related issues will be discussed in the present paper in the light of Islam.

Automatic Generation of Shared Hardware Design for Multiple Application Circuits

Field Programmable Gate Arrays (FPGAs) are popular due to their programming flexibility and ease of design modification. However, the benefits of reconfigurability and reusability of FPGAs are also responsible for their inefficiencies compared to Application Specific Integrated Circuits (ASICs). FPGAs suffer huge gap in terms of area, power and speed as compared to ASICs. Despite their inefficiency, FPGAs are still replacing ASICs in mid and low-volume products. This thesis explores the design space between FPGA and ASIC. Several architectural modifications are proposed in the FPGA to get feasible architectures that lie between an ASIC and an FPGA. ThisthesisexploresthefeasibilityofSRAM-TablesharinginFPGAarchitectureswithlarger LUT sizes. SRAM-Table sharing based FPGA architecture allows sharing of SRAM-Table among NPN-equivalent functions, thus allowing reduction in the area as well as the numberofconfigurationbits.ToaccommodatethisconceptinexistingFPGAarchitecture,anew CLB architecture is proposed with LUT input sizes greater than four, higher degree of sharing, and more shared pairs. The CAD flow is also modified to efficiently map the netlists ontheproposedarchitecture.ExperimentalresultsonMCNCbenchmarkcircuitssuggestan overall area reduction of 7% while maintaining the same critical path delay and no compromise on FPGA programming flexibility. Manydigitalsystemsprovidemultiplebutcloselyrelatedfunctionalities,notallofthemare required simultaneously. Dedicated hardware solution for each functionality will waste too much silicon area. This work also explores shared hardware solution for a set of functionalities which will execute only one functionality at a time. The shared hardware solutions explored in this thesis are termed as ASIF++ and Multi-Circuit. A previously proposed technique named as Application Specific Inflexible FPGA (ASIF) is further enhanced to propose ASIF++. An ASIF is a customized design for a given set of application circuits, which is generated by significantly optimizing the routing resources ofanFPGA.ThisworkoptimizeslogicblocksofASIFusingSRAM-tablesharingtechnique. Moreover,SRAMsintheroutingnetworkareremovedbyapplyinggateinsertiontechnique. Thistechniquenotonlyreducesarea,butalsominimizesreconfigurationtime,bitstreamsize and size of external memory used to store circuit bitstreams. ASIF++ is 4∼9% area efficient than ASIF for group of 2-5 circuits. Thisthesisfurtherexploresthefeasibilityofsharedhardwaresolution.LogicblocksofASIF++ are further optimized to a shared hardware named as "Multi Circuit". It is a customized single platform shared ASIC for a known set of applications. Multi-circuit is primarily meant to be integrated as an embedded component in a larger design such as an SoC (System On Chip). Experiments reveal that Multi-Circuit is 73% ∼ 89% smaller than its corresponding FPGA design. Multi-Circuit is also 18%∼ 42% smaller than ASIF++. An automatic hardware generator is also presented that generates VHDL models of MultiCircuit and ASIF++, and bitstreams of the circuits mapped on them.