Universal Serial Bus (USB) is a serial connectivity standard that provides easy connection between all sorts of peripherals and host computer. Main purpose behind the development of USB standard is to replace many varieties of parallel and serial ports.USB 2.0 is the current serial connectivity solution that supports transfer rates up to 480 Mbps. With the development of USB 3.0 enabled products, this transfer rate will soon increase to 4.8 Gbps, tenfold higher transfer rate over USB 2.0. USB 3.0 (also branded as USB SuperSpeed) will be the next version of the Universal Serial Bus family. The goal of this research is to define and develop the macro-architecture and then micro-architecture (independent of languages) for the USB 3.0 host controller soft IP core. USB 3.0 is very current standard. Its technical specification revisions 1.0 released in November 2008. Standard define new dual-bus architecture that is fully compatible with USB 2.0. It offers more than 10 % high speed over USB 2.0?s and better power saving mechanism. Due to its complexity designing the architectural specification from technical specification will be a great challenge. Because of high speed and high performance, low power consumption would be a crucial design concern. The next optional step of this research would be the optimization of this architecture for power and speed. Once it has been done and verified according to given SuperSpeed USB technical specifications, optimization techniques would be applied to produce low power and highly efficient core for USB 3.0. Future work includes implementation and simulations of the host controller IP core. The architecture and the micro-architecture developed for this project will result in development of commercial soft IP core. It will serve as bases for creating several other products.