With the arrival of Chip Multi-Processors (CMPs), every processor has now built-in parallel computational power and that can be fully utilized only if the program in execution is written accordingly. Also existing memory system and parallel developments tools do not provide adequate support for general purpose multi-core programming and unable to utilize all available cores efficiently. This research is an attempt to come up with some solutions for the challenges that multi- core processing is currently facing. This thesis contributes by proposing a novel multi-level cache system design "LogN+1 and LogN cache Models" for multi-core processors. This new proposed cache system is based on binary tree data structure and can be replaced with the existing 3-level cache system in order to minimize memory contention related problems. This thesis also contributes by developing a new multi-thread parallel programming model, "SPC3 PM” (Serial, Parallel and Concurrent Core to Core Programming Model), for multi-core processors. The SPC3 PM is a serial- like task-oriented parallel programming model which consists of a set of rules for algorithm decomposition and a library of primitives to exploit thread-level parallelism and concurrency on multi-core processors. The programming model works equally well for different classes of problems including basic, complex, regular and irregular problems. Furthermore, a parallel trace-driven multi- level cache simulator "MCSMC" (Multi-level Cache Simulator for Multi-Cores) is also developed during this PhD research. It is a new addition in the family of cache simulators using that one can simulate the present 3-level cache system or any customized multi-level cache system. Its parallel execution makes it more efficient and less time consuming and its large set of input parameters also provides a wide range of simulation scenarios.