جسٹس بشیر احمد سعید
افسوس ہے چند ماہ ہوئے جسٹس بشیر احمد سعید صاحب کابھی کم وبیش ۸۴ برس کی عمر میں دل کا دورہ پڑنے سے ان کے وطن مدراس میں انتقال ہوگیا۔ مرحوم بڑے فعال ومتحرک اورسرگرم وپُرجوش مسلمان تھے انہوں نے مسلمانوں کی تعلیمی ترقی کے لیے مدراس میں وہی کیا جوڈاکٹر عبدالغفور نے کیرالا میں کیا تھا، ’’جنوبی ہند کے مسلمانوں کی تعلیمی انجمن‘‘کے صدر کی حیثیت سے انہوں نے مدراس میں دو عظیم الشان کالج تعمیر کرائے ایک لڑکوں کے لیے اوردوسرا لڑکیوں کے لیے، آج یہ دونوں کالج مدراس یونیورسٹی کے نمایاں اورترقی یافتہ کالج سمجھے جاتے ہیں۔
مرحوم آل انڈیا شخصیت کے بزرگ تھے، سالہا سال وہ علی گڑھ یونیورسٹی کی مرکز کونسل اور کورٹ کے نہایت بااثر اورفعال ممبر رہے، آل انڈیا مسلم مجلس مشاورت اورآل انڈیا مسلم پرسنل لابورڈ دونوں کے سرگرم رکن تھے۔ سرکاری ملازمت سے سبکدوشی کے بعد ان کے شب و روز قومی کاموں میں ہی بسر ہوتے تھے۔ نماز،روزہ کے بڑے پابند،قرآن مجید کی تلاوت ان کے مشاغل یومیہ میں شامل، ندوۃ المصنفین کے شروع سے معاون تھے، برہان بڑے شوق سے پڑھتے اوراس کی بڑی قدر کرتے تھے، غرض کہ بڑی خوبیوں اوراعلیٰ اخلاق و صفات کے بزرگ تھے۔ حق گوئی اورحق پژوہی ان کاجوہر فطری تھا، انگریزی کے بڑے اچھے مقرر تھے، اردو میں بھی اظہار مدعاپر قادر تھے، تقریر بڑے جوشیلے انداز میں کرتے تھے۔ اس میں شک نہیں کہ ان کا نفس وجود مسلمانوں کے لیے بڑی تقویت کاسبب تھا کیونکہ وہ قانون دان بھی تھے اورمسلمانوں کے سچے ترجمان ووکیل بھی۔ [جولائی۱۹۸۴ء]
This paper critically analyses pre-9/11 diasporic identity of Muslims living in the US as immigrants or expatriates depicted in The Reluctant Fundamentlist (TRF) and Home Boy (HB) authored by minority outgroup Muslims (MO). The pre-9/11 identity and image of Muslims has exacerbated from erotic, primitive, barbaric, ignorant, close-minded and semicitizen to maddened, fundamentalist, blood-thirsty and terrorist after the attacks. The study attempts a textual analysis of the novels in the light of Rosenau’s model (2003) of diasporic acculturation process and social identity theory (ST). Given this stereotyping, this study endeavours to dissect the pre-9/11approach Muslims immigrants adopt to negotiate their religious identity in the hostland: whether they are fanatic and diehard separatist or they are moderate and assimilative into the enlightened values of the West. Opposite to popular assumptions, the protagonists have been found very much assimilative and adoptive to the host culture and also adhere to their homeland culture as well.
This research thesis presents the assessment/determination of level of hazard/threat to emerging microelectronics devices in Low Earth Orbit (LEO) space radiation environment with different orbital parameters to predict the performance of onboard memories and/or random logic devices fabricated in 65 nm technology node. In this context, the various parameters for space radiation environment have been analyzed to characterize the ionizing radiation environment effects on proposed VLSI devices. The space radiation environment has been modeled in the form of particles trapped in Van-Allen Earth Radiation Belts (ERBs), Energetic Solar Particles Event (ESPE) and Galactic Cosmic Rays (GCRs) whereas its potential effects on Device- Under-Test (DUT) has been predicted in terms of Total Ionizing Dose (TID), Single-Event Effects (SEE) and Displacement Damage Dose (DDD). The required mitigation techniques including necessary shielding requirements to avoid undesirable effects of radiation environment at device level has been determined with assumed typical Aluminum shield thickness of 100 mils or 2.54 mm. In order to evaluate space radiation environment and analyze energetic particles effects on six transistors (6T) Static Random Access Memory (SRAM) bit-cell, Outil de Modélisation de l‟Environnement Radiatif Externe (OMERE) toolkit developed by Tests & Radiations (TRAD) company/organization located at Toulouse France was utilized. Therefore, this thesis focuses on the radiation response of 6T SRAM bit-cell circuits operating in radiation environment existing at LEO. The performance of bulk CMOS technology based devices was evaluated by characterizing its susceptibility to Single Event Upsets (SEUs). Further, the impact of technology scaling on SEU rates, Linear Energy Transfer (LET) threshold and area of cross-section per bit/device due to ionizing radiation environment at an altitude up to 1000 km was simulated. Due to irradiation of gate and drain regions of off-state NMOS transistor in SRAM bit cell with LET spectrum of particles transmitted through shielding, the magnitude and pulse duration of generated transient current translated to voltage pulses were analyzed. The sensitive strike locations for 65 nm SRAM bitcell were presented in SEU map whereas Cumulative Distribution Function (CDF) for upset probability regarding SEU occurrence was presented as a function of Vdmin i.e. minimum differential voltage between the internal complementary storage nodes of SRAM represented by Q Q (Q-bar). Finally, the SEU sensitive parameters required to predict SEU rate of on-board target device i.e. 65nm SRAM was calculated with typical Aluminum spot shielding using fully physical mechanism simulation. Moreover, contribution of Multiple Cell Upsets (MCUs) towards total SEU rate for 65nm SRAM bitcell was determined with Multi Scale Single Event Phenomenon Prediction Platform (MUSCA SEP3) toolkit The effect of TID on MOS devices in LEO environment to cause electrostatic potential variations and drain leakage current “Id” was determined with Genius device simulator module of Visual TCAD. Finally, effect of Displacement Damage Dose (DDD) was estimated for 1 MeV electron and 10 MeV protons fluence with the help of OMERE-TRAD toolkit. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Klayout, GDS2MESH, Visual TCAD/Genius, GSEAT/Visual Particle, runSEU and MUSCA SEP3 were utilized whereas LEO radiation environment assessment as well as single event upset rate prediction was accomplished with the help of OMERE-TRAD software.