عیدی
جب لوگ آسمان کی وسعتوں میں
ایک خم دار دھندلی سی لکیر تلاش کر رہے تھے
جو سب کے لیے باعث ِ مسرت تھی
مگر کسے خبر تھی
وہ شام میرے لیے غموں کے طوفان لانے والی ہے
اس لکیر کو دیکھتے ہوئے
میرے تصور میں بھی ایک نقطہ سا پھیلنے لگا
جو ایک مانوس صورت کا روپ دھار رہا تھا
چند قیمتی اذیت دہ لمحات میں ڈھلتی صورت
This research is focused on press-government relationship on the issue of ‘War on Terrorism’ (WoT) during the dictatorial regime led by the then military ruler General Pervez Musharraf who remained in power till 2008 in the Islamic Republic of Pakistan. Global war against terrorism, generally known as ‘war on terror’ was actually started by the United States of America in the aftermath of 9/11 episode in 2001. Pakistan, on US demand, had not only become an important ally of the grand alliance formed under the umbrella of the United States but had also adopted the role of a frontline state just to fight the war against terrorism (WoT) alongside the war allies. Generally mass media have the potential to influence public opinion and help reshape the states’ policies on different issues. Likewise, mass media of Pakistan also took an active part in the war either by going alongside the then dictatorial government or against it. This research is based on examining the way the Urdu language elite press, the most popular mass media of Pakistan, covered the dictatorial regime of President General Pervez Musharraf with regard to its policy on the issue of ‘WoT’. Main purpose of this study is to know the nature of relationship between the Urdu-language elite press and the dictatorial government of Gen Musharraf in Pakistan with regard to their policy positions on ‘WoT’ from 2001 to 2008. Three newspapers including daily Jang, daily Nawa-I-Waqt, and daily Pakistan, considered to be representatives of the Urdu-language elite press of Pakistan, were selected for this study. The method used to measure the phenomenon is called framing where contents of the selected dailies were measured both quantitatively and qualitatively. Data were collected through systematic sampling method, while coding sheet was used as a tool for data collection. Unsigned main editorials of the selected newspapers were analyzed to examine the nature of relationship existed between the two entities i.e. The Urdu-language elite press, and the dictatorial government of Gen Pervez Musharraf, on the issue of ‘WoT’ in Pakistan. The results revealed that the selected elite newspapers, in general, remained critical to the dictatorial regime on the issue of ‘WoT’. The findings also revealed that daily Nawa-I-Waqt remained highly critical to the government as compared to its other contemporaries i.e. Daily Jang, and daily Pakistan. It was also revealed that the Urdu-language elite press while framing the ‘War on Terror’ remained somewhat supportive and rarely neutral to the dictatorial regime on it policy on ‘WoT’.
This thesis presents a hardware based testing methodology for speeding up process of verification. With advent of VLSI technology the gate densities on a chip are increasing with rate predicted by Moor’s law. The designers are now mapping complex applications in silicon for enhanced performance and reduced cost. The testing of these designs is becoming more and more challenging. The simulation based testing is very slow and for moderately complex designs takes hours and even days to give decent coverage. The thesis presents novel methodology to test the design by inserting test logic in Hardware. The methodology best works for FPGA based verification. The design is first mapped on FPGA for functional verification. The thesis presents modules that are integrated with the DUTs and monitors the results for correctness. The model also provides white box testing whereby internal working of the design is exploited for exact location of a bug. The methodology also provides assertions based testing and provides coverage analysis of design for a set of test vectors. The thesis gives different examples of circuits that are tested using the proposed methodology. In-silicon White box verification with checkers and monitors holds a great potential in keeping pace with the rapid growth in VLSI technology. The basic idea of our proposed methodology can be termed as a hardware (tester circuitry) testing another hardware (Design under Test). The concept of an embedded layer of re-configurable/removable testing circuit or agent within the hardware of the DUT is proposed and experimented. Starting from simple combinational and sequential circuits to RISC processor and Medium Access Control (MAC) layer found in the IEEE 802.11e standard are tested through this methodology. Two main advantages have been observed: 1) The proposed methodology is found well suited for finding the root causes of the errors in the design under real time. 2) A considerable time saving is observed. The design which takes days in testing with simulation runs, gives equivalent results in minutes when it is run on FPGA prototype along with embedded test agent proposed in this thesis. When device is fully tested and ready for fabrication, this additional tester circuitry can be removed.