Logic Decomposition with Technology Mapping for Area and Delay Minimization in FPGA Design.

Thesis Info

Access Option

External Link

Author

Khalil-ur- Rehman

Supervisor

Abdul Qadeer Rajput; Bhawani Shankar Chowdhry

Department

Telecommunication & Control Engineering

Program

PhD

Institute

Mehran University of Engineering and Technology

Institute Type

Private

City

Jamshoro

Province

Sindh

Country

Pakistan

Thesis Completing Year

19-01-2007

Thesis Completion Status

Complete

Subject

Telecommunication & Control Engineering

Language

English

Link

http://prr.hec.gov.pk/jspui/bitstream/123456789/6614/1/3382H.pdf

Added

2021-02-17 19:49:13

Modified

2023-03-12 19:52:02

ARI ID

1676729163079

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